An All-Digital Phase-Locked Loop with High Resolution for Local On-Chip Clock Synthesis Oliver Schrape1, Frank Winkler2, Steffen Zeidler1, Markus Petri1, Eckhard Grass1, Ulrich Jagdhold1 International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2010)
Grenoble, France 10th September 2010 1
IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany
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2
HUB Institut für Informatik Rudower Chaussee 25 12489 Berlin
www.informatik.hu-berlin.de
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Outline •
Motivation
•
Phase-Locked Loops − Approaches − Structure of the proposed ADPLL
•
Chip Description − Control Unit (CU) − Digitally Controlled Oscillator (DCO) − Frequency Divider − Chip Layout
•
Comparison
•
Measurement Results
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Motivation
How to get fast clocks in a circuitry ?
Solution:
Some problems:
PLL (Phase-Locked Loop)
•Frequency limit of IO pads •EMI problems •Clock skew of extern generated clocks •Environmental effects IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany
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PLL – Traditional Approach PLL : Phase-Locked Loop Components Phase Frequency Detector (PFD), Loop Filter, Voltage Controlled Oscillator (VCO), Frequency Divider Advantages •High resolution •Low jitter •Low phase noise
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Disadvantages •Development time (costly) •Process dependency
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PLL – Digital Approach ADPLL : All-Digital Phase-Locked Loop Components: PFD, Control Unit, Digitally Controlled Oscillator (DCO), Frequency Divider Advantages •Shorter development time •Fast lock-in phase •More adaptable to other circuit technologies
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Disadvantages •Accuracy •Large jitter •Noisy
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ADPLL – Fundamental Functionality Functionality (simplified) 1. Compare phases of reference and feedback clock 2. Increase or decrease the control word ´w´ 3. Divide generated clock by (M,S)
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Control Algorithms (1) – linear / binary
• • •
ADPLL is initialized with the mean value of valid DCO frequencies Additional counter allows an adjustment every x reference cycle CU evaluates up/down signals of the PFD Control Unit
Advantage: • Few resources • Low complexity Complexity:
flag_u flag_d pwidth
OSC
cntx
Kp
cnt1 cnt2
+
Kd Ki
+
lin./bin.
w
PID/PID2
Disadvantage: • Long lock-in phase
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Control Algorithms (2) – PID Controllers
• •
Using a local ring oscillator to sample phase differences Additional counters measure the phase error
Advantage: • Short lock-in phase Disadvantage: • Many logic resources
Control Unit flag_u flag_d pwidth
OSC
cntx
Kp
cnt1 cnt2
+
Kd Ki
+
lin./bin.
w
PID/PID2
General PID Controller:
Innovation, smoothing with: IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany
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Control Algorithms – Matlab Model Simulation Frequency Histogram
ADPLL Frequencies
Frequency Histogram
ADPLL Frequencies
250
2 PID smoothed PID 1.8
200 1.6
Count Count
f f[GHz] [GHz]
150 1.4
1.2
100
1
50 0.8
0
0.8
1
1.2
1.4
1.6
1.8
2
0
50
f [GHz]
150 Reference Periods
200
250
300
Reference Periods
f [GHz] Algorithm
Area [mm²]
Power [µW]
Lock Time [cycles]
(non-)linear
0.024
0.5
500 – more than 1000
(smoothed) PID
0.108
32.25
< 50
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100
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Digitally Controlled Oscillator – Structure
Problem •Frequency range vs. resolution Innovation •Combining of three different approaches → Wide frequency range with high resolution
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Digitally Controlled Oscillator – Structure
•
Coarse-Tuning stage − Multiplexer structures (one-hot-coded) Resolution: > 300 ps
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[WASET ’08]
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Digitally Controlled Oscillator – Structure
•
•
Coarse-Tuning stage − Multiplexer structures (one-hot-coded) Resolution: > 300 ps Fine-Tuning stage − Bus keeper components (permutation) Resolution: 40 ps
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[WASET ’08]
[IAPCS ’2006]
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Digitally Controlled Oscillator – Structure
•
•
•
Coarse-Tuning stage − Multiplexer structures (one-hot-coded) Resolution: > 300 ps Fine-Tuning stage − Bus keeper components (permutation) Resolution: 40 ps Fine-Fine-Tuning stage − Parallel connected tri-states (n:m code) Resolution: < 5 ps
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[WASET ’08]
[IAPCS ’2006]
[ECCTD ’01]
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Digitally Controlled Oscillator – Properties
• • • •
Requires only 46 logic gates (37, +9 additional inverter/buffer) Resolution < 1 ps Linearized steps: 5 - 25 ps Range: 250 MHz – 1.3 GHz
Post Layout Simulation with parasitic RC: clk_dco = 1.27 GHz, Temp: 125 °C, VDD = 2.25 V IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany
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Frequency Divider
•
Contains optional 2:1 prescaler and dual modulus (4/5) divider
•
Swallow Counter switches dual modulus divider
•
Programmable over SPI interface
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Layout
• • •
3 power domains 1.6 mm x 1.6 mm size Macro blocks: DCO and LVDS interface
Test board
1.6 mm x 1.6 mm
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Properties – Comparison
Performance Parameter
Proposed ADPLL
[ICSS ’2003]
[ECCTD ’01]
[NCETET ’08]
Process
0.25 µm BiCMOS
0.35 µm CMOS
0.35 µm CMOS
0.18 µm CMOS
Core Area
0.81 mm2
0.71 mm2
0.07 mm2
0.0025 mm2
Gates (DCO)
46
> 100
128
-
Pwr. Dissip.
< 50 mW (@ 800 MHz)
100 mW (@ 500 MHz)
-
6.4 mW (-)
Min. Freq.
250 MHz
45 MHz
170 MHz
0.1 MHz
Max. Freq.
1.3 GHz
510 MHz
360 MHz
282 MHz
Lock-in Time
< 70 cycles
< 46 cycles
~ 60 cycles
< 5 cycles
Resolution
< 25 ps
< 5 ps
< 55 ps
--
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Measurement
Linear search algorithm, PLL locks at 560 MHz IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany
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Measurement – Simple Multiplexer Paths
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Conclusion
Done: •ADPLL with a wide frequency range and high resolution Combination of three different approaches leads to a good performance •ADPLL controllable with fast lock-in algorithm Modified (smoothed) PID algorithm was introduced
Future work: •Further measurements
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Thank you for your attention …
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